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low skew, 1-to-9 differential-to-lvcmos / lvttl zero delay buffer ics86953i-147 ics86953byi-147 revision b february 26, 2010 1 ? 2010 integrated device technology, inc. g eneral d escription the ics86953i-147 is a low voltage, low skew 1-to-9 differential-to-lvcmos/lvttl clock genera- tor. the pclk, npclk pair can accept most standard differential input levels. with output frequencies up to 175mhz, the ics86953i-147 is targeted for high per- formance clock applications. along with a fully integrated pll, the ics86953i-147 contains frequency configurable outputs and an external feedback input for regenerating clocks with ?zero delay?. f eatures ? nine single ended lvcmos/lvttl outputs; (8) clocks, (1) feedback ? pclk, npclk pair can accept the following differential input levels: lvpecl, cml, sstl ? maximum output frequency: pll mode, 175mhz ? vco range: 250mhz to 700mhz ? output skew: 75ps (maximum) ? cycle-to-cycle jitter: 50ps (maximum) ? static phase offset: 90ps 110ps ? 3.3v supply voltage ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages b lock d iagram hiperclocks? ic s 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view q1 v ddo q2 gnd q3 v ddo q4 gnd 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 ics86953i-147 q5 v ddo q6 gnd q7 v ddo mr/noe npclk v dda fb_clk nc nc nc nc gnd pclk gnd q0 v ddo qfb gnd pll_sel nbypass vco_sel p in a ssignment phase detector lpf vco 2 4 0 1 0 1 pclk npclk fb_clk vco_sel nbypass mr/noe pll_sel qfb q0:q6 q7 7 / 0 1
ics86953byi-147 revision b february 26, 2010 2 ? 2010 integrated device technology, inc. ics86953i-147 low skew, 1-to-9 differential-to-lvcmos / lvttl zero delay buffer t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 1v a d d r e w o p. n i p y l p p u s g o l a n a 2k l c _ b ft u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i k c o l c k c a b d e e f 6 , 5 , 4 , 3c nd e s u n u. t c e n n o c o n , 7 1 , 3 1 , 7 9 2 , 5 2 , 1 2 d n gr e w o p. d n u o r g y l p p u s r e w o p 8k l c pt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d l c e p v l g n i t r e v n i - n o n 9k l c p nt u p n i / p u l l u p n w o d l l u p . t u p n i k c o l c l a i t n e r e f f i d l c e p v l g n i t r e v n i v o t d e s a i b y l l a n r e t n i o d d . 2 / 0 1e o n / r mt u p n in w o d l l u p n e h w . e l b a n e t u p t u o w o l e v i t c a . t e s e r r e t s a m h g i h e v i t c a e r a s t u p t u o e h t d n a t e s e r e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . ) z i h ( d e t a t s - i r t . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e e r a s t u p t u o e h t 7 2 , 3 2 , 9 1 , 5 1 , 1 1v o d d r e w o p. s n i p y l p p u s t u p t u o , 8 1 , 6 1 , 4 1 , 2 1 6 2 , 4 2 , 2 2 , 0 2 , 4 q , 5 q , 6 q , 7 q 0 q , 1 q , 2 q , 3 q t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o k c o l c 4 1 . e c n a d e p m i t u p t u o l a c i p y t 8 2b f qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c k c a b d e e f 4 1 . e c n a d e p m i t u p t u o l a c i p y t 0 3l e s _ l l pt u p n ip u l l u p , k l c p s t c e l e s , w o l n e h w . h g i h n e h w o c v s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k l c p n 1 3s s a p y b nt u p n ip u l l u p. e d o m s s a p y b n i , w o l n e h w . h g i h n e h w l l p s t c e l e s 2 3l e s _ o c vt u p n ip u l l u p . w o l n e h w 1 o c v s t c e l e s . h g i h n e h w 2 o c v s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r t able 3a. o utput c ontrol p in f unction t able t able 3b. p rogrammable o utput f requency f unction t able s t u p n i n o i t a r e p o s t u p t u o s s a p y bl e s _ l l pl e s _ o c v7 q : 0 q , b f q 0xx s s a p y b r e d i v i d d n a l l p : e d o m t s e tk l c 10 0 s s a p y b l l p : e d o m t s e t4 / k l c 10 1 s s a p y b l l p : e d o m t s e t8 / k l c 110 e d o m l l p4 / o c v 111 e d o m l l p8 / o c v t u p n is t u p t u o e o n / r m7 q : 0 q , b f q 1z i h 0d e l b a n e l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k c d p ) t u p t u o r e p ( e c n a t i c a p a c n o i t a p i s s i d r e w o pv a d d v , o d d v 5 6 4 . 3 =572 1f p r t u o e c n a d e p m i t u p t u o 4 1
ics86953byi-147 revision b february 26, 2010 3 ? 2010 integrated device technology, inc. ics86953i-147 low skew, 1-to-9 differential-to-lvcmos / lvttl zero delay buffer t able 4a. p ower s upply dc c haracteristics , v dda = v ddo = 3.3v5%, t a = -40c to 85c t able 4b. lvcmos / lvttl dc c haracteristics , v dda = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v a d d e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i a d d t n e r r u c y l p p u s g o l a n a 0 2a m i o d d t n e r r u c y l p p u s t u p t u o 5 7a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i t u p n i e g a t l o v h g i h , s s a p y b n , l e s _ o c v e o n / r m , l e s _ l l p 2v d d 3 . 0 +v k l c _ b f2v d d 3 . 0 +v v l i t u p n i e g a t l o v w o l , s s a p y b n , l e s _ o c v e o n / r m , l e s _ l l p 3 . 0 -8 . 0v k l c _ b f3 . 0 -3 . 1v i n i t n e r r u c t u p n i 0 2 1 a v h o e g a t l o v h g i h t u p t u oi h o a m 0 2 - =v d d 6 . 0 -v v l o e g a t l o v w o l t u p t u oi l o a m 0 2 =6 . 0v a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 47.9c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 4c. lvpecl dc c haracteristics , v dda = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i n i t n e r r u c t u p n i 0 2 1 a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o c 5 . 0 + d n gv d d 5 8 . 0 -v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i .
ics86953byi-147 revision b february 26, 2010 4 ? 2010 integrated device technology, inc. ics86953i-147 low skew, 1-to-9 differential-to-lvcmos / lvttl zero delay buffer t able 6. ac c haracteristics , v dda = v ddo = 3.3v5%, t a = -40c to 85c t able 5. pll i nput r eference c haracteristics , v dda = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f f e r y c n e u q e r f e c n e r e f e r t u p n i 5 7 1z h m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o e d o m l l p1 = l e s _ o c v5 2 . 1 35 . 7 8z h m e d o m l l p0 = l e s _ o c v0 5 . 2 65 7 1z h m e d o m s s a p y b 0 0 2z h m t d p ; y a l e d n o i t a g a p o r p 1 e t o n k l c p n , k l c p5 . 24s n t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o e g d e g n i s i r n o d e r u s a e m t av d d 2 / 5 7s p t ) c c ( r e t t i j5 e t o n ; r e t t i j e l c y c - o t - e l c y c 0 5s p ) ? ( t5 , 3 e t o n ; t e s f f o e s a h p c i t a t s 0 2 -0 90 0 2s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 10 0 7s p c d oe l c y c y t u d t u p t u o 7 40 53 5% t k c o l e m i t k c o l l l p 0 1s m t n e 4 e t o n ; e m i t e l b a n e t u p t u o 6s n t s i d 4 e t o n ; e m i t e l b a s i d t u p t u o 7s n d e h s i l b a t s e s i h i c h w , e g n a r e r u t a r e p m e t g n i t a r e p o t n e i b m a d e i f i c e p s e h t r e v o d e e t n a r a u g e r a s r e t e m a r a p l a c i r t c e l e : e t o n t e e m l l i w e c i v e d e h t . m p f l 0 0 5 n a h t r e t a e r g w o l f r i a e s r e v s n a r t d e n i a t n i a m h t i w t e k c o s t s e t a n i d e t n u o m s i e c i v e d e h t n e h w . s n o i t i d n o c e s e h t r e d n u d e h c a e r n e e b s a h m u i r b i l i u q e l a m r e h t r e t f a s n o i t a c i f i c e p s 0 5 f o n o i t a n i m r e t : e t o n o tv o d d . 2 / v o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n o d d . t u p t u o e h t f o 2 / . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n v t a d e r u s a e m o d d . 2 / l a n g i s t u p n i k c a b d e e f e g a r e v a e h t d n a k c o l c e c n e r e f e r t u p n i e h t n e e w t e b e c n e r e f f i d e m i t e h t s a d e n i f e d : 3 e t o n . e l b a t s s i y c n e u q e r f e c n e r e f e r t u p n i e h t d n a d e k c o l s i l l p e h t n e h w . n o i t c u d o r p n i d e t s e t t o n . n o i t a z i r e t c a r a h c y b d e e t n a r a u g e r a s r e t e m a r a p e s e h t : 4 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 5 e t o n
ics86953byi-147 revision b february 26, 2010 5 ? 2010 integrated device technology, inc. ics86953i-147 low skew, 1-to-9 differential-to-lvcmos / lvttl zero delay buffer 3.3v o utput l oad ac t est c ircuit d ifferential i nput l evel o utput s kew c ycle - to -c ycle j itter o utput d uty c ycle /p ulse w idth /p eriod o utput r ise /f all t ime p hase j itter & s tatic p hase o ffset p arameter m easurement i nformation scope qx lvcmos gnd 1.65v5% -1.65v5% q0:q7, qfb ? ? ? ? v ddo 2 v ddo 2 v ddo 2 t cycle n t cycle n+1 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t sk(o) v ddo 2 v ddo 2 qy v cmr cross points v pp gnd pclk npclk v dd q0:q7, qfb t pd v ddo 2 pclk npclk t period t pw t period odc = v ddo 2 x 100% t pw q0:q7, qfb p ropagation d elay ? ? t (?) v oh v ol v oh v ol v ddo 2 fb_clk pclk npclk (where t (?) is any random sample, and t (?) mean is the average of the sampled cycles measured on controlled edges) t jit(?) = t (?) ? t (?) mean = phase jitter v dda , v ddo qx 20% 80% 80% 20% t r t f q0:q7, qfb
ics86953byi-147 revision b february 26, 2010 6 ? 2010 integrated device technology, inc. ics86953i-147 low skew, 1-to-9 differential-to-lvcmos / lvttl zero delay buffer a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perfor- mance, power supply isolation is required. the ics86953i-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dda and v ddo should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. fig- ure 1 illustrates this for a generic v dd pin and also shows that v dda requires that an additional10 resistor along with a 10f bypass capacitor be connected to the v dda pin. p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering v ddo v dda 3.3v 10 10f .01f .01f figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single- ended swing and v dd are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line f igure 2. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels impedance. for most 50 applications, r3 and r4 can be 100 . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single ended signaling, the noise rejection benefits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal.
ics86953byi-147 revision b february 26, 2010 7 ? 2010 integrated device technology, inc. ics86953i-147 low skew, 1-to-9 differential-to-lvcmos / lvttl zero delay buffer lvpecl c lock i nput i nterface the pclk /npclk accepts lv pecl, cml, sstl and other dif- ferential signals. both differential inputs must meet the v pp and v cmr input requirements. figures 3a to 3e show interface ex- amples for the pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. f igure 3a. pclk/npclk i nput d riven b y a cml d river f igure 3b. pclk/npclk i nput d riven b y a b uilt -i n p ullup cml d river f igure 3c. pclk/npclk i nput d riven b y a 3.3v lvpecl d river pclk/npclk 2.5v zo = 60 ohm sstl hiperclocks pclk npclk r2 120 3.3v r3 120 zo = 60 ohm r1 120 r4 120 2.5v f igure 3e. pclk/npclk i nput d riven b y a n sstl d river hiperclocks pclk npclk pclk/npclk 3.3v r2 50 r1 50 3.3v zo = 50 ohm cml 3.3v zo = 50 ohm 3.3v hiperclocks pclk npclk r2 84 r3 125 input zo = 50 ohm r4 125 r1 84 lvpecl 3.3v 3.3v zo = 50 ohm 3.3v r5 100 - 200 3.3v 3.3v hiperclocks pclk npclk r1 125 pclk/npclk r2 125 r3 84 c1 c2 zo = 50 ohm r4 84 zo = 50 ohm r6 100 - 200 3.3v lvpecl f igure 3d. pclk/npclk i nput d riven b y a 3.3v lvpecl d river with ac c ouple 3.3v 3.3v cml built-in pullup r1 100 pclk npclk hiperclocks pclk/npclk zo = 50 ohm zo = 50 ohm
ics86953byi-147 revision b february 26, 2010 8 ? 2010 integrated device technology, inc. ics86953i-147 low skew, 1-to-9 differential-to-lvcmos / lvttl zero delay buffer vdd (u1-23) zo = 50 ohm r7 10 - 15 r4 50 c2 0.1uf c11 0.01u r1 36 vdd c5 0.1uf r3 50 r9 1k r8 1k c4 0.1uf r5 50 c6 (option) 0.1u (u1-19) (u1-27) r2 36 zo = 50 vcc (u1-11) r6 1k c3 0.1uf lvpecl driv er c1 0.1uf u1 ics86953i-147 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 9 vdda fb_clk nc nc nc nc gnd pclk mr/noe vddo q7 gnd q6 vddo q5 gnd q4 vddo q3 gnd q2 vddo q1 vco_sel nbypass pll_sel gnd qfb vddo q0 gnd npclk zo = 50 vdd zo = 50 ohm c16 10u (u1-15) vdd r10 1k l ayout g uideline the schematic of the ics86953i-147 layout example is shown in figure 4a. the ics86953i-147 recommended pcb board layout for this example is shown in figure 4b. this layout example is used as a general guideline. the layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the p.c. board. f igure 4a. ics86953i-147 lvcmos z ero d elay b uffer s chematic e xample
ics86953byi-147 revision b february 26, 2010 9 ? 2010 integrated device technology, inc. ics86953i-147 low skew, 1-to-9 differential-to-lvcmos / lvttl zero delay buffer other signals c5 c16 r7 50 ohm trace vdd via 50 ohm trace r1 gnd c3 pin 1 u1 r2 vcca c2 c11 c4 c1 f igure 4b. pcb b oard l ayout f or ics86953i-147 the following component footprints are used in this layout example: all the resistors and capacitors are size 0603. p ower and g rounding place the decoupling capacitors as close as possible to the power pins. if space allows, placement of the decoupling capacitor on the component side is preferred. this can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. maximize the power and ground pad sizes and number of vias capacitors. this can reduce the inductance between the power and ground planes and the component power and ground pins. the rc filter consisting of r7, c11, and c16 should be placed as close to the v dda pin as possible. c lock t races and t ermination poor signal integrity can degrade the system performance or cause system failure. in synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. any ringing on the rising or falling edge or excessive ring back can cause system failure. the shape of the trace and the trace delay might be restricted by the available space on the board and the component location. while routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. ? the 50 output traces should have same length. ? avoid sharp angles on the clock trace. sharp angle turns cause the characteristic impedance to change on the transmission lines. ? keep the clock traces on the same layer. whenever pos- sible, avoid placing vias on the clock traces. placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. ? to prevent cross talk, avoid routing other signal traces in parallel with the clock traces. if running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. ? make sure no other signal traces are routed between the clock trace pair. ? the series termination resistors should be located as close to the driver pins as possible.
ics86953byi-147 revision b february 26, 2010 10 ? 2010 integrated device technology, inc. ics86953i-147 low skew, 1-to-9 differential-to-lvcmos / lvttl zero delay buffer r eliability i nformation t ransistor c ount the transistor count for ics86953i-147 is: 1758 t able 7. ja vs . a ir f low t able for 32 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50. 1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39. 4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
ics86953byi-147 revision b february 26, 2010 11 ? 2010 integrated device technology, inc. ics86953i-147 low skew, 1-to-9 differential-to-lvcmos / lvttl zero delay buffer p ackage o utline - y s uffix for 32 l ead lqfp t able 8. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -0 1 . 0
ics86953byi-147 revision b february 26, 2010 12 ? 2010 integrated device technology, inc. ics86953i-147 low skew, 1-to-9 differential-to-lvcmos / lvttl zero delay buffer t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this pr oduct is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without addition al processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instrumen ts. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a pe r u t a r e p m e t 7 4 1 - i y b 3 5 9 6 87 4 1 i b 3 5 9 6 8 s c ip f q l d a e l 2 3y a r tc 5 8 o t c 0 4 - t 7 4 1 - i y b 3 5 9 6 87 4 1 i b 3 5 9 6 8 s c ip f q l d a e l 2 3l e e r & e a t 0 0 0 1c 5 8 o t c 0 4 - f l 7 4 1 - i y b 3 5 9 6 8l 7 4 1 i b 3 5 9 6 s c ip f q l d a e l 2 3 , e e r f - d a e ly a r tc 5 8 o t c 0 4 - t f l 7 4 1 - i y b 3 5 9 6 8l 7 4 1 i b 3 5 9 6 s c ip f q l d a e l 2 3 , e e r f - d a e ll e e r & e a t 0 0 0 1c 5 8 o t c 0 4 -
ics86953byi-147 revision b february 26, 2010 13 ? 2010 integrated device technology, inc. ics86953i-147 low skew, 1-to-9 differential-to-lvcmos / lvttl zero delay buffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d b 1 t 2 t 2 2 7 9 & 8 . 9 n i p o t n w o d l l u p / p u l l u p d e d d a c d e g n a h c - e l b a t s c i t s i r e t c a r a h c n i p n i . l a c i p y t f p 4 o t . x a m f p 4 m o r f t i m i l c o t l a c i p y t f p 7 d n a . n i m f p 5 d e d d a d p . . d 3 d n a c 3 e r u g i f d e t a d p u . t u o y a l d r a o b b c p d n a e n i l e d i u g t u o y a l d e d d a 3 0 / 8 2 / 0 1 b 2 t2 r d e d d a - e l b a t s c i t s i r e t c a r a h c n i p t u o . w o r4 0 / 3 2 / 4 b 6 t 9 t 4 6 7 2 1 . e t o n l a m r e h t d e d d a - e l b a t s c i t s i r e t c a r a h c c a . n o i t c e s s l e v e l d e d n e e l g n i s t p e c c a o t t u p n i l a i t n e r e f f i d e h t g n i r i w d e t a d p u . n o i t c e s e c a f r e t n i t u p n i k c o l c l c e p v l d e t a d p u r e b m u n r e d r o / t r a p e h t m o r f x i f e r p s c i e h t d e v o m e r - e l b a t o f n i g n i r e d r o . g n i k r a m e e r f - d a e l d e d d a . n m u l o c . t e e h s a t a d f o r e t o o f / r e d a e h d e t a d p u 0 1 / 6 2 / 2
sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt techical support netcom@idt.com +480-763-2056 6024 silver creek valley road san jose, ca 95138 ics86953i-147 low skew, 1-to-9 differential-to-lvcmos / lvttl zero delay buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performace, is subject to change without notice. performance s pecifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the in formation contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitablity of idt?s products for any particular purpose, a n implied warranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device techology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used her ein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2010. all rights reserved. www.idt.com

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